this post was submitted on 14 Jun 2024
236 points (98.8% liked)
Technology
58133 readers
4751 users here now
This is a most excellent place for technology news and articles.
Our Rules
- Follow the lemmy.world rules.
- Only tech related content.
- Be excellent to each another!
- Mod approved content bots can post up to 10 articles per day.
- Threads asking for personal tech support may be deleted.
- Politics threads may be removed.
- No memes allowed as posts, OK to post as comments.
- Only approved bots from the list below, to ask if your bot can be added please contact us.
- Check for duplicates before posting, duplicates may be removed
Approved Bots
founded 1 year ago
MODERATORS
you are viewing a single comment's thread
view the rest of the comments
view the rest of the comments
Not good. That bench is from a BananaPi with the same SoC, via reddit (sorry).
Maybe about an A55. If you want a performant RISC-V you've gotta wait until stuff leaks out of the European Supercomputer stuff onto the market though that one probably won't have good IPC either unless it's vector, or maybe one of the big chip design companies will grace us with a chip with a RISC-V insn decoder.
I think those will have to have fairly good IPC, otherwise they won't be able to keep the array processors fed with work.
Guess we'll see.
You can keep the array processors fed with low IPC and frequency by having absolutely massive vector lengths, the engineering for that kind of processor isn't in the pipeline, branch prediction etc. it's in the APUs and how to stream data into them. Much more like GPUs, in fact RISC-V has instructions for gather/scatter.
Disagree. You quite often have a fair degree of scaler code in between portions which are embarrassingly parallel. If you don't have a decent scaler core you are destined to be become bottlenecked on them. It's not that different to a CPU / GPU pairing. If one is under powered, it determines the speed of the overall system.
If you look at what a company like Tenstorrent is doing, they are designing high performance Risc-V cores as a side aspect of their main goal of doing array processors. The reason is because they couldn't find scaler cores on the market with enough performance to not bottleneck the system.