You might be interested in the YouTube channel ProjectsInFlight, which is currently trying to build a DIY solution for fabbing simple ICs in their garage & documenting the process on YouTube.
this post was submitted on 18 Oct 2023
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CMOS silicon logic can be chemically "printed" using photolithography and commercially available mercury lamps. From the wikipedia article, if I read between the lines those are good down to feature sizes of about 1 micron (1.0µM or 1000nm), limited of course by the accuracy of your wafer setups between processes and the printing of your lithography plates. this is the process used to produce the Intel 80486 which fit 1 million transistors on a chip. seems that laser lithography using KrF lasers can be good down to much smaller but your litho plates become the limiting factor.
so, conservatively- 1µm features would be attainable for a sort of "home brew" startup with little to no venture funding but the correct industrial knowledge. with more funding though i'd guess older laser lithography machines would be attainable on the used market and potentially usable down to 0.4µm or smaller.
Realistically, you can't really compete in a market where ASML is the monopolist. Not because ASML is an ass, but simply because building just a single factory costs billions. Intel regularly invests 10 billion or more in just a single factory that doesn't even have all the necessary tools in-house to produce a chip end to end.
Smaller manufacturers usually serve the long tail, that is rather old process nodes for use cases where bleeding edge performance isn't needed. Bosch for example had its own manufacturing branch.
Also bleeding-edge processes mean smaller, thinner gates. That's what gives them the fast switching speeds, but it reduces the max allowable voltage. For parts that need to handle more than 1.8V or so a modern 5nm process will just end up using bigger gates than the process is optimized for. May as well go with an older process (bigger minimum gate size) that's better suited to switching the voltage needed. For Bosch (automotive parts, power tools, etc) they're making a lot of parts with really big output transistors (switching 14V, 48V, etc) and not super high-performance processors.
The big disadvantage with particularly old processes is that they used smaller wafers. So fewer chips per wafer processed, meaning lower overall yields and higher price/chip. The switch from 200mm wafers to 300mm in 1999 meant the wafer area increased by a factor of 2.25! 300mm wafers also required fully-automated factories due to the weight of a wafer carrier (a front opening wafer pod, or FOUP, is 7-9kg when loaded with 25 wafers), which save on labor costs. So processes older than 1999 (around the 180nm node) are sometimes not worth it even for power electronics.
Sam Zeloof (http://sam.zeloof.xyz/) has been working in the area of DIY semiconductor fabrication, and has successfully fabricated working ICs (from 6 - 100 transistors). He's done an incredible job at reaching ~1970's technology levels in a home lab.
Another example of DIY fabrication: https://hackaday.com/2010/03/10/jeri-makes-integrated-circuits/ Jeri Ellsworth made her own silicon inverter.
These examples are still very small-scale compared to even simple microprocessors, etc - but it's fascinating to see this level of technology becoming more accessible.
Theres plenty of smaller, lower volume silicon fabs doing larger scale work, like Cmos 1micron and some doing sub micron down to what was cutting edge ~15 years ago.
Honetly kinda crazy that only one manufacturer can do the current modern stuff, but barely anything other than high end CPU need to be that small.