this post was submitted on 22 Oct 2024
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RISC-V Announces Ratification of the RVA23 Profile Standard (riscv.org)
submitted 2 weeks ago by RayJW@sh.itjust.works to c/hardware@lemmy.world
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Crossposted from https://lemmy.ml/post/21673583

RISC-V International, the global standards organization, today announced that the RVA23 Profile is now ratified. RVA Profiles align implementations of RISC-V 64-bit application processors that will run rich operating systems (OS) stacks from standard binary OS distributions. RVA Profiles are essential to software portability across many hardware implementations and help to avoid vendor lock-in. The newly ratified RVA23 Profile is a major release for the RISC-V software ecosystem and will help accelerate widespread implementation among toolchains and operating systems.

Each Profile specifies which ISA features are mandatory or optional, providing a common target for software developers. Mandatory extensions can be assumed to be present, and optional extensions can be discovered at runtime and leveraged by optimized middleware, libraries, and applications.

Key Components of RVA23 Include:

  • Vector Extension: The Vector extension accelerates math-intensive workloads, including AI/ML, cryptography, and compression / decompression. Vector extensions yield better performance in mobile and computing applications with RVA23 as the baseline requirement for the Android RISC-V ABI.
  • Hypervisor Extension: The Hypervisor extension will enable virtualization for enterprise workloads in both on-premises server and cloud computing applications. This will accelerate the development of RISC-V-based enterprise hardware, operating systems, and software workloads. The Hypervisor extension will also provide better security for mobile applications by separating secure and non-secure components.
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[–] RayJW@sh.itjust.works 2 points 2 weeks ago (1 children)

My understanding is, that the 1.0 spec for the extension was basically finalized in 2021 and CPUs using it are already available. Now it's just fully ratified. Also, while it might seem like RISC-V is “behind” compared to AVX-512 for x86_64 or SVE for ARM, this fundamentally differs from these SIMD Instructions. They talk more about it in this article SIMD Instructions Considered Harmful. So, this is not merely RISC-V playing catch-up, but also trying a “new” (the idea is actually old and how things used to be done) ways to make a more sustainable ISA.

[–] Alphane_Moon@lemmy.world 1 points 2 weeks ago

Thanks for sharing!